1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of detecting degradation in photolithography processes based upon scatterometric measurements of grating structures, and a device comprising such structures.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 11A of a semiconducting substrate or wafer 11 comprised of doped-silicon. In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting substrate. The substrate 11 may be doped with either N-type or P-type dopant materials, for example. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modem semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modem devices. For example, gate electrodes may now be patterned to a width 12 that is approximately 0.18 xcexcm (1800 xc3x85), and further reductions are planned in the future. As stated previously, the width 12 of the gate electrode 14 corresponds approximately to the channel length 13 of the transistor 10 when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Thus, there is a great desire for a method that may be used to accurately, reliably and repeatedly form features to their desired critical dimension, i.e., to form the gate electrode 14 to its desired critical dimension 12.
Photolithography is a process typically employed in semiconductor manufacturing. Photolithography generally involves forming a layer of photoresist material (positive or negative) above one or more layers of material, e.g., polysilicon, silicon dioxide, etc., that are desired to be patterned. Thereafter, a pattern that is desired to be formed in the underlying layer or layers of material is initially formed in the layer of photoresist using an appropriate stepper tool and known photolithographic techniques, i.e., an image on a reticle in the stepper tool is transferred to the layer of photoresist. Then, the layer of photoresist is developed so as to leave in place a patterned layer of photoresist substantially corresponding to the pattern on the reticle. This patterned layer of photoresist is then used as a mask in subsequent etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features, that are to be replicated in an underlying process layer. The features in the patterned layer of photoresist also have a critical dimension, sometimes referred to as a develop inspect critical dimension (DICD).
More particularly, in one illustrative embodiment, modern photolithography processes generally involve the steps of: (1) applying a layer of photoresist above a wafer, typically accomplished by a spin-coating process; (2) pre-baking (or soft-baking) the layer of photoresist at a temperature of approximately 90-120xc2x0 C. to reduce the level of solvents in the layer of photoresist and to improve the adhesion characteristics of the photoresist; (3) performing an exposure process, wherein a pattern is projected onto the layer of photoresist through a reticle used in a stepper tool to create a latent image in the layer of photoresist; (4) performing a post-exposure bake on the layer of photoresist at a temperature approximately 5-15xc2x0 C. higher than the pre-bake process; (5) performing a develop process to turn the latent image in the layer of photoresist into the final resist image; and (6) performing a postbake process (or hard-bake) at a temperature of approximately 125-160xc2x0 C. to remove residual solids, improve adhesion, and to increase the etch resistance of the photoresist. These process steps are well known to those skilled in the art and, thus, will not be described herein in any greater detail.
Further background for the present invention will now be described with reference to FIGS. 2A-2B. As shown in FIG. 2A, a process layer 15 is formed above a semiconducting substrate 11 (or other previously-formed process layer), and a layer of photoresist material (positive or negative) 17 is formed above the process layer 15. The process layer 15 is meant to be illustrative of any type of material that may be patterned using known photolithographic and etching techniques.
Using known photolithographic techniques, the layer of photoresist material 17 is patterned to define a plurality of photoresist features 17A that are intended to be used as a mask in patterning the underlying process layer 15. See FIG. 2B. However, for a variety of reasons, the photolithography process may be incomplete and result in residual amounts of photoresist material 19 remaining between the photoresist features 17A. In the industry, this situation is sometimes referred to as photoresist xe2x80x9cscumming.xe2x80x9d Such scumming may be the result of a variety of factors, e.g., low stepper exposure dose, improper focus, insufficient develop time, etc. Additionally, the profile of the features 17A may also be degraded, as indicated by the dashed lines 21 in FIG. 2B, as part of the scumming phenomenon. Moreover, the degree of photoresist scumming may vary, e.g., the photoresist material between the features 17A may be partially removed to expose portions of the underlying process layer 15, or scumming may be so severe that the underlying process layer 15 is not exposed between the features 17A.
Photoresist scumming can cause many problems in subsequent manufacturing operations. For example, the ability to completely etch the underlying process layer 15 may be hampered due to the presence of the residual photoresist material 19, i.e., etching of the process layer 15 may be incomplete. As a result, device performance may be adversely impacted, and/or wafers may have to be re-worked to correct problems caused by photoresist scumming. Moreover, photoresist scumming becomes even more problematic as device feature sizes continue to decrease (with resulting increased density). That is, as device features continue to decrease and packing density continues to increase, photoresist scumming is more likely to occur. Lastly, photoresist scumming may not be uniform across the entire surface of the wafer, i.e., scumming may only occur in certain areas of the wafer.
The present invention is directed to a method and device that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to various methods of detecting degradation in photolithography processes based upon scatterometric measurements of grating structures, and a device comprising such structures. In one illustrative embodiment, the method comprises providing a wafer comprised of a plurality of grating structures, each of the grating structures being comprised of a plurality of features, each of the grating structures having a different critical dimension, illuminating at least one of the grating structures, measuring light reflected off of at least one of the grating structures to generate an optical characteristic trace for the grating structure, and determining the presence of residual photoresist material between the features of the grating structure by comparing the generated optical characteristic trace to at least one optical characteristic trace from a library. In some embodiments, the grating structures are arranged in a linear array. In further embodiments, at least one and, in some cases, a plurality of grating structures have a critical dimension that is less than an anticipated range of critical dimensions for integrated circuit devices to be formed on a wafer.
In another illustrative embodiment, the method comprises providing a wafer comprised of a plurality of grating structures, each of the grating structures being comprised of a plurality of spaced-apart photoresist features, each of the grating structures having a different spacing between the photoresist features, at least one of the grating structures having a spacing between the photoresist features that is less than an anticipated range of critical dimensions for integrated circuit devices to be formed on a wafer, illuminating at least one of the plurality of grating structures, measuring light reflected off of at least one of the grating structures to generate an optical characteristic trace for the at least one grating structure, and determining the presence of residual photoresist material between the features of the at least one grating structure by comparing the generated optical characteristic trace to at least one optical characteristic trace from a library.
In a further embodiment, the device comprises a wafer and a plurality of grating structures formed above the wafer, each of the grating structures having a different critical dimension, and at least one of the grating structures having a critical dimension that is less than an anticipated range of critical dimensions for integrated circuit devices to be formed on a wafer.